1. Field of the Invention
The present invention relates to the forming of integrated circuits. More specifically, the present application relates to the forming of cavities in insulating layers.
2. Description of the Related Art
In many integrated devices, in particular in optical devices, it is desirable to form cavities in insulating layers. Such cavities are especially used to obtain a maximum isolation.
FIGS. 1A to 1C illustrate, in partial simplified cross-section view, different steps of a known method for forming a cavity in an insulating layer.
As illustrated in FIG. 1A, the upper portion of an integrated circuit 1 is covered with an insulating layer 3 itself covered with an insulating layer 5. Portion 1 generally corresponds either to a metallization level, or to the semiconductor substrate in which active devices are formed. Layers 3 and 5 are made of different materials selectively etchable with respect to each other. For example, portion 1 is a single-crystal silicon substrate, layer 3 is a silicon oxide layer (SiO2), and layer 5 is a silicon nitride layer (Si3N4).
At the next steps illustrated in FIG. 1B, a dry etching of layer 5 and a selective wet etching of layer 3 by means of a same mask 7, are successively performed. An opening 9 is thus formed, which exhibits in upper layer 5 a substantially straight, vertical shape, which widens in layer 3. The dry etching is generally performed by means of a carbon tetrafluoride plasma (CF4). The wet etching is performed by means of a solution selectively etching the sole layer 3, without etching layer 5.
Then, as illustrated in FIG. 1C, an insulating layer 11 is deposited to seal the lips of opening 9 of FIG. 1B while maintaining a cavity 13 free.
Another disadvantage lies in the difference in optical properties between layers 3 and 5. When the cavities are formed in the transparent portion of an optical device such as an image sensor or an imager, this difference affects the device operation all the more as the silicon nitride used as layer 5 is not transparent.
Another disadvantage of such a method lies in the fact that the shape given to the cavity is set and cannot be selected.
Further, it should be noted that opening 9 exhibits an abrupt change of slope at the interface between layers 3 and 5—an abrupt widening in layer 3—which translates on deposition of sealing layer 11 by the forming of angle cavities 15. As will be exposed subsequently, such angle cavities 15 may be undesirable in optical devices.
To have cavities in a transparent insulating layer, another cavity-forming method has been provided.
FIG. 2 illustrates in partial simplified cross-section view an intermediary step of another cavity-forming method. The step of FIG. 2 corresponds to the step of FIG. 1B of the first method.
Upper layer 21 of an integrated circuit is covered with a silicon oxide layer 23 doped by means of phosphorus (P+). Layer 23 is covered with an undoped silicon oxide layer 25. Layer 23 is doped, generally in situ, at a concentration ranging between 1017 and 3×1018 at/cm3.
An etching capable of forming a vertical well, shown in dotted lines, is performed by means of a mask 27 illustrated in dotted lines in layers 23 and 25. This etching is a dry etch performed by means of a fluorocarbon plasma such as a carbon tetrafluoride plasma (CF4).
After removal of mask 27, the structure is dipped into a hydrofluoric acid bath generally intended for the cleaning of the polymer residues of mask 27. Then, doped silicon oxide layer 23 is etched. This etching is stronger than the corresponding etching of upper layer 25 illustrated by the difference between the dotted lines and the full lines delimiting the upper portion of opening 29.
A profile similar to that of FIG. 1C comprising a wide lower opening topped with an opening of small dimensions is then found again. The method carries on with the sealing of the opening lips to keep a cavity in the lower portion.
However, a disadvantage of such a method lies in the etching of layer 25 on etching of layer 23. The real dimensions of opening 29 are increased with respect to those of mask 27. This poses problems in the sealing operation. In particular, if opening 29 is too large in its upper portion, the subsequently deposited sealing material partially fills the lower portion of the opening and the resulting cavity exhibits small dimensions with respect to cavity 13 of FIG. 1C.
Another disadvantage lies in the fact that the obtained cavity exhibits angle cavities 15 such as the cavity (13, FIG. 1C) obtained with the first known method.